This invention relates to sense amplifiers and, more particularly, to sensing circuits of single-ended bit lines in arrays of semiconductor memory cells.
In semiconductor memory cell arrays, sense amplifiers are commonly used to determine the logic state of the memory cells in the arrays. Each cell is accessed by a plurality of word and bit lines which are conventionally arranged perpendicularly to each other. In the integrated circuit conductive lines, typically termed bit lines, carry the bit information representing the logic state of a memory cell from (and to) the memory cell when address signals engage decoder circuits which electrically connect the selected memory cell to a sense amplifier by one or two bit line(s) which then reads the logic state of the cell. Of the plurality of memory cells connected to the bit line(s), the decoder circuits send a signal to the word line to the selected memory cell make the electrical connection to the bit line(s), while signals to the word lines to the other memory cells physically connected to the bit line ensure that those memory cell are not electrically connected.
In memory cells in which the logic state is stored as the difference between two signals, such as in an SRAM (Static Random Access Memory) cell, the sense amplifier uses the two complementary signals from a selected memory cell over two bit lines to switch the sense amplifier into one state or another in a read operation. For memory cells in which the logic state is stored as a single signal, such as a DRAM (Dynamic Random Access Memory) cell, the sense amplifier compares the voltage of the single signal carried over a single, or alternatively termed single-ended, bit line from the selected memory cell against a reference voltage to determine the logic state in the selected memory cell.
Hence a reference voltage must be generated for sensing the logic state of memory cells over a single, or single-ended, bit lines. The reference voltage should be such that the sense amplifier can properly determine the logic state, i.e., “1” or “0”, of the selected memory cell. However, variations of the semiconductor manufacturing processes adversely affect the performance of a preset reference voltage. It would be preferable that a reference voltage generating circuit be tunable to compensate for manufacturing process variations to allow a sense amplifier to more accurately determine the logic states of memory cells. Furthermore, the reference voltage generating circuit should be small and compact to occupy a minimal amount of valuable space on the integrated circuit substrate surface.